Document Type Master's Dissertation Author Lambrechts, Johannes Wynand firstname.lastname@example.org URN etd-11112009-190546 Document Title Phase noise reduction of a 0.35 μm BiCMOS SiGe 5 GHz Voltage Controlled Oscillator Degree MEng Department Electrical, Electronic and Computer Engineering Supervisor
Advisor Name Title Dr S Sinha Supervisor Keywords
- phase noise
- voltage controlled oscillator
- Silicon Germanium
- performance trade-offs
- LC oscillator
- active circuit
- analogue integrated circuit
- bipolar CMOS
- single sideband
- heterojunction bipolar transistor
- tail-current suppression
Date 2009-11-11 Availability unrestricted Abstract
The research conducted in this dissertation studies the issues regarding the improvement of phase noise performance in a BiCMOS Silicon Germanium (SiGe) cross-coupled differential-pair voltage controlled oscillator (VCO) in a narrowband application as a result of a tail-current shaping technique. With this technique, low-frequency noise components are reduced by increasing the signal amplitude without consuming additional power, and its effect on overall phase noise performance is evaluated. The research investigates effects of the tail-current as a main contributor to phase noise, and also other effects that may influence the phase noise performance like inductor geometry and placement, transistor sizing, and the gain of the oscillator.
The hypothesis is verified through design in a standard 0.35 μm BiCMOS process supplied by Austriamicrosystems (AMS). Several VCOs are fabricated on-chip to serve for a comparison and verify that the employment of tail-current shaping does improve phase noise performance. The results are then compared with mathematical models and simulated results, to confirm the hypothesis.
Simulation results provided a 3.3 dBc/Hz improvement from -105.3 dBc/Hz to -108.6 dBc/Hz at a 1 MHz offset frequency from the 5 GHz carrier when employing tail-current shaping. The relatively small increase in VCO phase noise performance translates in higher modulation accuracy when used in a transceiver, therefore this increase can be regarded as significant. Parametric analysis provided an additional 1.8 dBc/Hz performance enhancement in phase noise that can be investigated in future works. The power consumption of the simulated VCO is around 6 mW and 4.1 mW for the measured prototype. The circuitry occupies 2.1 mm2 of die area.
Copyright © 2009, University of Pretoria. All rights reserved. The copyright in this work vests in the University of Pretoria. No part of this work may be reproduced or transmitted in any form or by any means, without the prior written permission of the University of Pretoria.
Please cite as follows:
Lambrechts, JW 2009, Phase noise reduction of a 0.35 μm BiCMOS SiGe 5 GHz Voltage Controlled Oscillator, MEng dissertation, University of Pretoria, Pretoria, viewed yymmdd < http://upetd.up.ac.za/thesis/available/etd-11112009-190546/ >C10/116/gm
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