Title page for ETD etd-09132010-162013


Document Type Master's Dissertation
Author Veale, Gerhardus Ignatius Potgieter
Email gert.veale@gmail.com
URN etd-09132010-162013
Document Title Low phase noise 2 GHz Fractional-N CMOS synthesizer IC
Degree MEng
Department Electrical, Electronic and Computer Engineering
Supervisor
Advisor Name Title
Dr S Sinha Supervisor
Keywords
  • CML-to-CMOS converter
  • CML flicker noise
  • Fractional-N
  • CMOS PFD
  • CML PFD
  • CML 4-bit counter
  • CML
  • CML 2/3-Prescaler
  • SSB phase noise
  • pulse-swallow counter
  • low division
  • programmable modulus accumulator
  • high voltage charge-pump
  • in-band phase noise
Date 2010-09-02
Availability unrestricted
Abstract

Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs. The research in this dissertation differs from convention, with the aim of implementing a synthesizer IC in a more convenient, low-cost Si-based CMOS process. A collection of techniques to push towards the noise and frequency limits of CMOS processes, and possibly other IC processes, is then one of the research outcomes.

In a synthesizer low N-divider ratios are important, as high division ratios would amplify in-band phase noise. The design methods deployed as part of this research achieve low division ratios (4 ≤ N ≤ 33) and a high phase comparison frequency (>100 MHz). The synthesizer IC employs a first-order fractional-N topology to achieve increased frequency tuning resolution. The primary N-divider was implemented utilising current mode logic (CML) and the fractional accumulator utilising conventional CMOS. Both a conventional CMOS phase frequency detector (PFD) and a CML PFD were implemented for benchmarking purposes. A custom-built 4.4 GHz synthesizer circuit employing the IC was used to validate the research.

In the 4.4 GHz synthesizer circuit, the prototype IC achieved a measured in-band phase noise plateau of L( f ) = -113 dBc/Hz at a 100 kHz frequency offset, which equates to a figure of merit (FOM) of -225 dBc/Hz. The FOM compares well with existing, but expensive, SiGe and GaAs HBT processes. Total IC power dissipation was 710 mW, which is considerably less than commercially available GaAs designs. The complete synthesizer IC was implemented in Austriamicrosystems‟ (AMS) 0.35 μm CMOS process and occupies an area of 3.15 x 2.18 mm2.

2010, University of Pretoria. All rights reserved. The copyright in this work vests in the University of Pretoria. No part of this work may be reproduced or transmitted in any form or by any means, without the prior written permission of the University of Pretoria.

Please cite as follows:

Veale, GIP 2010, Low phase noise 2 GHz fractional-N CMOS synthesizer IC, MEng dissertation, University of Pretoria, Pretoria, viewed yymmdd < http://upetd.up.ac.za/thesis/available/etd-09132010-162013/ >

C10/542/gm

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