Document Type Master's Dissertation Author Opperman, Tjaart Adriaan Kruger URN etd-04082009-171225 Document Title A 5 GHz BiCMOS I/Q VCO with 360° variable phase outputs using the vector sum method Degree MEng Department Electrical, Electronic and Computer Engineering Supervisor
Advisor Name Title Dr S Sinha Supervisor Keywords
- vector sum method
- variable gain amplifier
- inductor capacitor
- phase noise
- silicon germanium
- digital-to-analogue converter
- integrated circuit
- radio frequency
- local oscillator
- Gilbert mixer
- Bipolar CMOS
- voltage controlled oscillator
- phase shifter
- phased array antenna
Date 2009-04-17 Availability unrestricted AbstractThis research looks into the design of an integrated in-phase/quadrature (I/Q) VCO operating at 5 GHz. The goal is to design a phase shifter that is implemented at the LO used for RF up conversion. The target application for the phase shifter is towards phased array antennas operating at 5 GHz. Instead of designing multiple VCOs that each deliver a variety of phases, two identical LC-VCOs are coupled together to oscillate at the same frequency and deliver four outputs that are 90 ° out of phase. By varying the amplitudes of the in-phase and quadrature signals independently using VGAs before adding them together, a resultant out-of-phase signal is obtained. A number of independently variable out-of-phase signals can be obtained from these 90 ° out-of-phase signals and this technique is better known as the vector sum method of phase shifting. Control signals to the inputs of the VGAs required to obtain 22.5 ° phase shifts were designed from simulations and are generated using 16-bit DACs.
The design is implemented and manufactured using a 0.35 µm SiGe BiCMOS process and the complete prototype IC occupies an area of 2.65 × 2.65 mm2. The I/Q VCO with 360 ° variable phase outputs occupies 1.10 × 0.85 mm2 of chip area and the 16-bit DAC along with its decoding circuitry occupies 0.41 × 0.13 mm2 of chip area.
The manufactured quadrature VCO was found to oscillate between 4.12 ~ 4.74 GHz and consumes 23.1 mW from a 3.3 V supply without its buffer circuitry. A maximum phase noise of -78.5 dBc / Hz at a 100 kHz offset and -108.17 dBc / Hz at a 1 MHz offset was measured and the minimum VCO figure of merit is 157.8 dBc / Hz. The output voltages of the 16 bit DAC are within 3.5 % of the design specifications. When the phase shifter is controlled by the 16 DAC signals, the maximum measured phase error of the phase shifter is lower than 10 %.
© University of Pretoria 2009
Filename Size Approximate Download Time (Hours:Minutes:Seconds)
28.8 Modem 56K Modem ISDN (64 Kb) ISDN (128 Kb) Higher-speed Access 00dissertation.pdf 4.38 Mb 00:20:16 00:10:25 00:09:07 00:04:33 00:00:23 01appendixA.pdf 5.39 Mb 00:24:58 00:12:50 00:11:14 00:05:37 00:00:28 02appendixB.pdf 4.25 Mb 00:19:40 00:10:07 00:08:51 00:04:25 00:00:22