Title page for ETD etd-02162006-121543


Document Type Master's Dissertation
Author Sinha, Saurabh
URN etd-02162006-121543
Document Title A Bluetooth single-chip frequency synthesizer
Degree MEng (Micro Electronic)
Department Electrical, Electronic and Computer Engineering
Supervisor
Advisor Name Title
Prof. M du Plessis
Keywords
  • ring oscillator
  • LC oscillator
  • single sideband (SSB) mixer
  • active on-chip inductor
  • phase locked loop (PLL)
  • frequency synthesizer
  • phase noise
  • spurious tones
  • loop filters
  • passive on-chip inductor
  • voltage controlled oscillator (VCO)
  • pn-junction varactor
Date 2005-01-15
Availability restricted
Abstract
The research conducted for this dissertation seeks to understand the issues associated with integrating a frequency synthesizer on to a single monolithic chip. The target application for the frequency synthesizer is Bluetooth wireless technology devices. Radios that comply with the Bluetooth wireless specification operate in the unlicensed, 2.4 GHz radio spectrum ensuring communication compatibility worldwide. These radios use a spread spectrum, frequency hopping, and full-duplex signal at up to 1600 hops/sec. The signal hops among 79 frequencies (2.402 - 2.480 GHz band) at 1 MHz intervals to give a high degree of interference immunity.

This research implements the required synthesizer by individually considering each sub-system and designing to meet the overall specifications for a dual-loop synthesizer. Such a dual-loop synthesizer consists of two VCOs: one operating at a higher frequency (with a narrow operating range) and another VCO operating at a lower frequency (with a wider operating range.) A LC based VCO is designed for the higher frequency loop, and the required inductor is implemented on-chip. The research considers the various issues related to on-chip inductor implementation, and also considers an active inductor as an option. The lower frequency loop is implemented with a ring-oscillator.

The design is completed for fabrication in a standard 0.35-Ám CMOS process without any external components. The computed phase noise is -84 dBc/Hz at 1000 kHz offset from a 2.4-GHz carrier. With an active chip area of 3.8 mm^2, the simulated chip consumes about 100 mW.

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