Title page for ETD etd-01242006-102128


Document Type Master's Dissertation
Author Chen, Yi-Ju
URN etd-01242006-102128
Document Title An integrated CMOS optical receiver with clock and data recovery Circuit
Degree MEng (Micro-Electronics)
Department Electrical, Electronic and Computer Engineering
Supervisor
Advisor Name Title
Prof M du Plessis
Keywords
  • phase-locked loop
  • oscillator
  • clock and data recovery circuit
  • inductive peaking
  • front-end
  • photodetector
  • optical receiver
  • frequency-locked loop
Date 2005-08-09
Availability unrestricted
Abstract
Traditional implementations of optical receivers are designed to operate with external photodetectors or require integration in a hybrid technology. By integrating a CMOS photodetector monolithically with an optical receiver, it can lead to the advantage of speed performance and cost.

This dissertation describes the implementation of a photodetector in CMOS technology and the design of an optical receiver front-end and a clock and data recovery system. The CMOS detector converts the light input into an electrical signal, which is then amplified by the receiver front-end. The recovery system subsequently processes the amplified signal to extract the clock signal and retime the data.

An inductive peaking methodology has been used extensively in the front-end. It allows the accomplishment of a necessary gain to compensate for an underperformed responsivity from the photodetector.

The recovery circuits based on a nonlinear circuit technique were designed to detect the timing information contained in the data input. The clock and data recovery system consists of two units viz. a frequency-locked loop and a phase-locked loop. The frequency-locked loop adjusts the oscillatorís frequency to the vicinity of data rate before phase locking takes place. The phase-locked loop detects the relative locations between the data transition and the clock edge. It then synchronises the input data to the clock signal generated by the oscillator.

A system level simulation was performed and it was found to function correctly and to comply with the gigabit fibre channel specification.

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